The present invention relates to solid-state imaging apparatus, and more particularly to the solid-state imaging apparatus using amplified MOS sensor.
In recent years, those solid-state imaging apparatus where a solid-state imaging device referred to as amplified MOS sensor is used as the solid-state imaging apparatus are mounted for example on power-saving type solid-state imaging apparatus for mobile-equipment or on high-resolution electronic still cameras. For the current solid-state imaging apparatus using amplified MOS sensor, methods are proposed in which a pixel area having a plurality of pixel cells arranged into a matrix is selected row by row so that photoelectric charge is converted into a voltage signal and read out through an amplification means contained in each pixel cell. At this time, while a bias current is supplied to the amplification means in each pixel cell through a column-by-column bias means, the influence of resistance component of ground wirings to which the bias means is connected is becoming not ignorable due to the continuous development to increase the number of pixels. For example, at a pixel cell on which an intense light (i.e. a high-luminance light) is incident, an output level of the pixel cell is significantly lowered and goes beyond a normal operation range of the bias means whereby the bias current does not flow any longer. This change in electric current at the bias means causes a bias current of other pixel cell on the same one row to be increased through a resistance component occurring on the ground wiring. Because of this change in bias current, a white transverse stripe-like image is resulted on the pixel row that contains the pixel cell on which the intense light is incident.
Various methods have been proposed to reduce such white transverse stripe. FIG. 1 is a circuit diagram showing construction of the solid-state imaging apparatus disclosed in Japanese Patent Application Laid-Open 2001-230974, being an example of the solid-state imaging apparatus where such white transverse stripe is reduced. The solid-state imaging apparatus shown in FIG. 1 includes: a pixel section 2 having pixel cells 1 (Pixel11 to Pixel33) that are two-dimensionally arranged into row direction and column direction (3 rows by 3 columns in this case); a vertical scanning section 3 for selecting row to be read out of the pixel section 2; vertical signal lines V1 to V3 for outputting pixel signal column by column from the pixel section 2; a bias current section 4 for supplying an electric current to the amplification means of the pixel cell 1 through the vertical signal lines V1 to V3; and a clip section 5 for causing the potential of the vertical signal lines V1 to V3 to be clipped so that the bias current section 4 is restricted to its normal operation range.
Each of the pixel cells 1 indicated by Pixel11 to Pixel33, when Pixel11 is taken as representative, includes: a photodiode PD11 serving as photoelectric conversion section; a floating diffusion FD11 for converting electric charge accumulated at the photodiode PD11 into a voltage; a reset transistor M211 for resetting the floating diffusion FD11 to a pixel power supply voltage VDD; an amplification transistor M311 for amplifying the voltage of the floating diffusion FD11; and a row select transistor M411 for selecting each row. The pixel section 2 is constructed such that the pixel cells 1 are placed side by side into 3 rows by 3 columns as described above. The vertical scanning section 3 is to output reset control signals φ RS1 to φ RS3 for controlling operation of the reset transistors M211 to M233 and row select control signals φ SEL1 to φ SEL3 for controlling operation of the row select transistors M411 to M433.
The bias current section 4 includes: a bias current setting input transistor M40 of which the gate and drain are connected to a reference current input terminal Iref; and transistors for bias current M41 to M43 of which the drain is connected to the vertical signal line V1 to V3, the gate to the gate of the above described bias current setting input transistor M40, and the source to a ground line. It is to supply a bias current Ibias to the amplification transistor of the pixel cells of selected pixel row selected at the vertical scanning section 3. The clip section 5 includes: transistors for clipping M51 to M53 of which the gate is connected to a clip voltage input terminal Vclip; and clip select transistors M54 to M56 of which the gate is connected to a clip control signal φ clip. It is to cause the potentials of the vertical signal lines V1 to V3 not to fall below an output level corresponding to the clip voltage input terminal Vclip.
An operation of the solid-state imaging apparatus shown in FIG. 1 will now be described. A case is supposed here that a first row from the upper side of the pixel section 2 is selected by the vertical scanning section 3 and that an intense light is incident on the pixel Pixel21 while light is scarcely incident on the pixels Pixel11 and Pixel3l. Since the pixels Pixel11 and Pixel31 in this case are in substantially the same condition, only the operation of the pixels Pixel11 and Pixel21 will be described. At first when light is incident on the photodiodes PD11 and PD21, photoelectric charges are accumulated at the photodiodes PD11 and PD21. Since the first row from the upper side of the pixel section 2 is being selected by the vertical scanning section 3, the select transistors M411 and M421 are turned ON as the row select signal φ SEL1 attains H level so that the amplification transistor M311 and the vertical signal line V1, and the amplification transistor M321 and the vertical signal line V2 are respectively connected whereby pixel signals of the pixels of the first row are read out. Further, due to H level of the clip control signal φ clip at the clip section 5, the clip select transistors M54 to M56 are also turned ON so that the clip transistor M51 is connected to the vertical signal line V1 and the clip transistor M52 to the vertical signal line V2, respectively. Here, the amplification transistor M311 and the clip transistor M51 as well as the amplification transistor M321 and the clip transistor M52 constitute a differential input construction where their sources are connected in common.
In this case, when light is scarcely incident on the pixel Pixel11 so that a light signal potential Vsig(FD11) of the floating diffusion FD11, i.e. the gate potential of the amplification transistor M311 is higher than the clip voltage Vclip that is the gate potential of the clip transistor M51, the clip transistor M51 is turned OFF and an output level corresponding to the light signal potential Vsig(FD11) of the floating diffusion FD11 is obtained on the vertical signal line V1. At this time, the output level of the vertical signal line V1 is an output level with which the bias current transistor M41 operates in a saturation region.
In the case where an intense light is incident on the pixel Pixel21 so that a light signal potential Vsig(FD21) of the floating diffusion FD21, i.e. the gate potential of the amplification transistor M321 is lower than the clip voltage Vclip that is the gate potential of the clip transistor M52, on the other hand, the amplification transistor M321 is turned OFF. The vertical signal line V2 then attains an output level corresponding to the clip voltage Vclip which is applied on the gate of the clip transistor M52 and does not fall below [Vclip−VGS(M52)]. Here, VGS(M52) is a gate-source voltage of the clip transistor M52. At this time, by setting the clip voltage Vclip to a suitable value, the bias current transistor M42 always operates in a saturation region so that the bias current Ibias is kept at a constant level.
As the above, since the vertical signal line V2 does not fall below an output level corresponding to the clip voltage input terminal Vclip even when the intense light is incident on the pixel Pixel21, the change in the output current Ibias of the bias current transistor M42 is suppressed so that the white transverse stripe does not occur.